The present invention generally relates to semiconductor devices and production methods thereof, and more particularly to a semiconductor device such as an electrically programmable read only memory (EPROM) which has upper and lower conductor layers having an insulator layer interposed therebetween and a method of producing such a semiconductor device including a process of patterning the upper and lower conductor layers by a kind of self-alignment.
With the increase in the integration density of semiconductor devices, there are now more strict demands to reduce the area occupied by each element of the semiconductor device. In order to satisfy such demands and to form fine patterns with a high accuracy, it is becoming essential to make a self-alignment patterning using an anisotropic dry etching.
First, a description will be given of an example of a conventional method of patterning using the anisotropic dry etching. In FIG. 1A, a lower layer 20 is formed on a substrate 80, and an upper layer 30 is formed on the lower layer 20 and the substrate 80. When a resist mask layer 60 is formed on the upper layer 30 and a patterning is made using anisotropic dry etching, a portion of the upper layer 30 remains at the stepped portion as a side wall portion 31 as shown in FIG. 1B. This side wall portion 31 is often used effectively as an insulator layer, a mask which is used when implanting impurities and the like.
On the other hand, there are cases where the upper and lower layers 30 and 20 are made of materials having large etching rates. In such cases, when the upper and lower layers 30 and 20 shown in FIG. 2A are patterned by a kind of self-alignment, a side wall portion 32 may remain after the patterning as shown in FIG. 2B. This side wall portion 32 may come off the substrate 80 during subsequent processes and adhere on another part of the substrate 80. In other words, the side wall portion 32 may become a contamination source and interfere or prevent the formation of fine patterns on the surface of the substrate 80.
A more detailed description will be given of the above described problems encountered in storage and control electrodes of an EPROM, by referring to FIG. 3. FIG. 3 shows a cross section of an essential part of a storage transistor in the so-called FLOTOX type EPROM. A storage electrode 52 which is made of a polysilicon layer, for example, is formed on a semiconductor substrate 1 via a gate insulator layer 51. A control electrode 53 is formed on the storage electrode 52 via an insulator layer 54 which is made of Si.sub.3 N.sub.4, for example. A source/drain region 56, an interlayer insulator 57 and an interconnection layer 58 are formed as shown.
A stepped portion of some sort always exists on the substrate 1 (semiconductor chip). For example, an alignment mark which is made of polysilicon as in the case of the storage electrode 52 is formed at a peripheral region of the chip, and a stepped portion is formed by the provision of this alignment mark. For this reason, when the insulator layer 54 and an upper polysilicon layer which constitutes the control electrode 53 are successively formed on the alignment mark and the upper polysilicon layer and a lower polysilicon layer which constitutes the alignment mark are patterned by self-alignment at the same time as forming of the storage and control electrodes 52 and 53, a Si.sub.3 N.sub.4 side wall portion is formed as described above. If a stepped portion exists in the lower polysilicon layer within the chip region, an isolated Si.sub.3 N.sub.4 side wall portion is formed similarly.
Therefore, when an isolated side wall portion is generated in the above described manner, there is a problem in that it is impossible to pattern the storage and control electrodes 52 and 53 by self-alignment unless a measure is taken to prevent the side wall portion from coming off the substrate in a latter process. As a result, the integration density cannot be improved.
A Japanese Laid-Open Patent Application No. 1-276737 proposes a method of producing a semiconductor device, in which at least a peripheral portion of a first layer, which constitutes a mark pattern, is covered by a second layer. However, there is no suggestion in this proposal to eliminate the problems of the side wall portion when patterning the upper and lower polysilicon layers by self-alignment.
When patterning the stacked structure which includes a lower layer, an interlayer insulator and an upper layer which are formed in this sequence, the interlayer insulator is etched by an anisotropic etching. If the stacked structure were etched by an isotropic etching, the edge of the interlayer insulator would be etched further towards the inside compared to the upper and lower layers. For this reason, isotropic etching cannot be applied to the interlayer insulator, and anisotropic etching must be used for the interlayer insulator. A side wall portion of the interlayer insulator will be generated by anisotropic etching.
In order to prevent the generation of the side wall portion of the interlayer insulator, it is possible to take one of the following three measures. According to a first measure, the edge of the lower layer is completely covered by the interlayer insulator and the upper layer covers the interlayer insulator in its entirety. According to a second measure, the edge of the lower layer is patterned to have a downwardly spreading taper, and the edge of the lower layer is completely covered by the interlayer insulator which is covered by the upper layer in its entirety. According to a third measure, the edge of the lower layer is not self-aligned, and the edges of the interlayer insulator and the upper layer are located on the inside of the edge of the lower layer.
The first and third measures require positioning margin for the upper and lower layers, and it is impossible to form fine patterns. On the other hand, it is difficult to control the width of the lower layer when the second measure is taken, and the width of the lower layer cannot be made extremely small because of the tapered edge.
Therefore, in order to form fine patterns, it is necessary to pattern the upper and lower layers by a self-alignment. In addition, to prevent the problem introduced when the second measure is taken, the lower layer must be patterned by anisotropic etching.